Workshop

How HLS and SystemC is Delivering on its Promise of Design and Verification Productivity

Stuart Swan, Mike Meredith, Matt Bone, Rangharajan Venkatesan

Date & Time

Mon, March 2, 2020

03:30 pm – 05:00 pm

Abstract

HLS has long promised that it could deliver dramatic productivity by raising the level of abstraction but there have always been questions regarding the fit of this technology and the results that it could achieve vs hand-coded RTL and what an overall HLS design and verification methodology would look like.

This 90-minute tutorial will begin with an introduction to the SystemC Synthesizable Subset and an introduction to basic concepts of how HLS works to go from SystemC/C++ description to quality RTL. It will then leave a majority of the time for the audience to hear from two leading semi-conductor vendors about real-world use-cases and the results they have achieved; Intel and NVIDIA.

Matt Bone of Intel will describe their challenges and successful techniques for design space exploration and tuning of algorithmic and fabric-oriented designs.

Rangharajan Venkatesan of NVIDIA will describe their open-source HLS library, MatchLib, and present a case study for fast prototyping of a Machine Learning accelerator using object-oriented HLS methodology.


Presenters

Stuart Swan

A Siemens Business

Mike Meredith

Cadence Design Systems, Inc.

Matt Bone

Intel Corp.
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Document

Slides - How HLS and SystemC is Delivering on its Promise of Design and Verification Productivity (application/pdf) Download (22510.674 KB)

Presentation Chair

Mike Meredith

Cadence Design Systems, Inc.

Date & Time

Mon, March 2, 2020

03:30 pm – 05:00 pm